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EDAPS 2019

Monday, December 16, 2019 - 8:00 am / Wednesday, December 18, 2019 - 5:00 pm CET

EDAPS 2019

 IEEE Electrical Design of Advanced Packaging and Systems

The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)symposium, a flagship event in the Asia-Pacific region, has consistently served as a platform for dissemination of latest research in the areas of electrical design of chip, package, and system. Designers and researchers across the world come forth to share and discuss their work on all aspects of electrical packaging including modeling, design and simulation, fabrication and characterization. This symposium consists of technical paper presentation, poster sessions, industry exhibits, workshops, and tutorials.

The southern city of Kaohsiung is Taiwan’s largest port, its second-largest city, and center of the country’s heavy and petrochemical industries. Despite this, it is a modern urban landscape of airy cafes, wide streets, waterside parks, public transport, bicycle lanes and cultural venues that have embraced and re-imagined the city’s manufacturing past. There are also two swimming beaches within the city area, and 1000 hectares of the almost-pristine forest right on its doorstep.

EDAPS is sponsored by the IEEE Electronics Packaging Society.

EDAPS will be an excellent forum to highlight the latest advances in the high-speed and high-performance semiconductor industry. Engineers and researchers will engage in the 3 full-day conferences and workshop, to be held during December 16-18 in Kaohsiung. The forum offers a great opportunity for sponsorships and for the related companies to build their brands in this leading international platform.


  1. 3D-ICs/TSVs/Interposers
  2. Testing on 3D-IC and SiP
  3. Signal and Thermal Integrity
  4. Power Integrity/Power Distribution Networks (PDNs)/Ground Noise
  5. Computational Electromagnetics and Multi-physics Methods for SI/PI/TI Analysis
  6. Thermal Management Design for 3D-ICs and SiP
  7. Design and Modeling for High-speed Channels and Interconnects
  8. High-speed serial links jitter budgeting
  9. Jitter segregation algorithms and tools
  10. Time / Frequency Domain Measurement Techniques
  11. Power supply induced jitter and transfer functions.
  12. Nanoelectronics for 3D-ICs and SiP
  13. Machine Learning applied to package
  14. Active Devices and Circuit Modeling Technologies
  15. Electronic Packages, SiP/ SoP
  16. IC and Package Level EMC
  17. Antennas in Packages (AiP)
  18. RF/mm-wave and THz Packages
  19. Miniaturized and Embedded Passives
  20. Power Electronic Packages
  21. Advanced Simulation Tools and CAD
  22. Substrate Technology for Packages and PCBs
  23. Electrical Design of Flexible Devices and Sensing
  24. 2-D Materials for 3D-ICs and SiP
  25. 3-D ICs and SiP Reliability
  26. Electrical Design for 5G Wireless Communication
  27. DDR’s Signal and Power integrity considerations
  28. Others


  1. Prospective authors should submit a three-page manuscript by August 5, 2019
  2. Notification about acceptance will be given by September 20, 2019.
  3. Accepted papers will be reproduced as-is in the Conference Proceedings.
  4. In addition, authors of accepted papers will be invited to submit an extended version of their manuscript for a Special Section based on EDAPS-2019 to be published in the IEEE Transactions on components, packaging and manufacturing technology (T-CPMT).
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Monday, December 16, 2019 - 8:00 am CET
Wednesday, December 18, 2019 - 5:00 pm CET
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No. 266號, Chenggong 1st Road
Kaohsiung City, Qianjin District 801 Taiwan
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