Validation ASIC Space Applications Video Presentation.
MEWS , The 29th Microelectronics Workshop
Agustín Coello Vera from Alter Technology, during the presentation at MEWS , Tsukuba International Congress Center in Japan.
Traditionally ASICs (and FPGAs) used in space were manufactured using Rad-Hard technologies and designed with special libraries.
AS CMOS Technologies became denser (beyond the 180 nm node) it was realized that it was no longer affordable to change the semiconductor technology and that hardening had to be assured by other means.
With DSM , access to the technology has become even harder for space users.
As a result, today, in many cases (specially for smaller users) each box in the design flow below is assured by a different entity.
ALTER has implemented an independent global solution which takes over right after foundry.
What about space requirements?
For space most of what it has been learned by the designers, coming from other sectors, does not apply.
In the space, the radiation, thermal and mechanical requirements are quite different to anything known to ASIC designers.
Highly skilled designer will fail out in the SPACE unless the entire supply chain is properly addressed.