When selecting a laboratoy to fulfil testing, calibration or measurement needs, you need to be sure that they can supply you with accurate and reliable results. The technical competence of a laboratory depends on a number of factors including: the qualifications, training and experience of the staff the right equipment –properly calibrated and maintained adequate quality assurance procedures proper sampling practices appropriate testing procedures valid test methods traceability of measurements to national standards accurate recording and reporting procedures suitable testing facilities
The use of differential (or balanced) digital and analog circuits for information processing has increased in recent years . When transmitting high-speed electrical signals, both the electromagnetic (EM) fields generated by the transmitted signals and the ground plane return current might cause electrical interference on adjacent circuits. Moreover, with the trend of digital systems to move to lower operating voltage, logic signal swing and noise margin also decrease, thus deteriorating the noise immunity of the digital system.
Surface contamination involving micrometric particles, microbiological agents, molecular adsorbate and others, represent a significant hazard in many areas of industry. For instance, a high level cleanliness is a critical requirement that any EEE device has to fulfil at any development stage: from the fabrication process of single components, before encapsulation, to the final PCB assembly. This is so because micro- and nanometric foreign materials may produce corrosion, electrochemical migration, delamination or cause parametric changes. These and other contamination-induced phenomena are responsible for impairment performance, incorrect test results and, most importantly, the catastrophic fail of complete units. Beside such adverse effects, non-conducting contaminants can also contribute to electrostatic discharge, particularly in the space environment. Therefore this is a vital concern for different national and international aerospace, military and space agencies, which have adopted strict protocol about this issue.
ECSS-Q-ST-70-38C standard defines precisely the technical requirements and quality assurance provisions for the manufacture and verification of high-reliability electronic circuits based on surface mounted device (SMD) and mixed technology.
The procurement, evaluation, screening and lot acceptance of RF devices in leadless SMD packages to be used in spacecraft applications show unexpected difficulties whenever degolding or retinning processes are required. This is associated to the induced lack of coplanarity in the contacts after those. ECSS-Q-ST-60-13C requires pure tin contacts to be retinned. Additionally, the assem bly processes selected by the OEMs requires gold finish to be removed and replaced by tin-lead alloys.
A compact balanced-to-balanced diplexer composed of two balanced bandpass filters is proposed in this letter. The balanced filters are implemented using compact edge-coupled square split-ring resonators. The design methodology is based on the standard coupled-resonators filter synthesis procedure.
The scope of Element Evaluation is to assess the reliability of a individual device to be used as add-on component in an hybrid assembly. Element Evaluation cover electrical, physical and environmental (depending of required class level) performance of the add-on components to guarantee the space use of the tested devices.
New space missions include more extreme requirements of storage and operational temperatures and vacuum conditions exceeding standard -55ºC / +125ºC conditions Miniaturization implies increase higher power dissipation and hence max junction and PCB temperatures.
For decades, military/space electrical, electronic, and electromechanical (EEE) parts have proved to be suitable for use in military and space applications. [NASA's Office of Safety & Mission Assurance (OSMA) evaluates newly available and advanced electronic parts for programs and projects under its EEE Parts program.]
Traditionally ASICs (and FPGAs) used in space were manufactured using Rad-Hard technologies and designed with special libraries. AS CMOS Technologies became denser (beyond the 180 nm node) it was realized that it was no longer affordable to change the semiconductor technology and that hardening had to be assured by other means. With DSM , access to the technology has become even harder for space users. As a result, today, in many cases (specially for smaller users) each box in the design flow below is assured by a different entity. ALTER has implemented an independent global solution which takes over right after foundry.