Design of a Latch-Up Effects Monitoring System in ADC Converters

Assigned Scholarship

Design of a Latch-Up effects monitoring system in ADC converters.

The objective of this project is to design a set-up of control and monitoring of effects type SEL (Single Event Latch-up) when an ADC is exposed to heavy ion radiation.

The project is framed within an ambitious framework for the development of robust design protocols for the characterization of SEE effects (Single Event Effects) in several types of ADC converters, one of which is called Latch-Up.

Latch-up (interlocking) is a term used in the world of integrated circuits to describe a particular type of short circuit that can occur in an electrical circuit. More specifically it is the inadvertent creation of a parasitic structure which disables its correct functioning, and gives rise to a possible damage, producing a current conduction through a path not designed for it, being able to destroy the device.

The parasitic structure is normally equivalent to a thyristor (or controlled silicon rectifier, SCR), a PN junction structure (PNPN) that acts as a PNP and an NPN (bipolar junction transistor). During the interlock, when one of the transistors is driving, the other starts doing it too. Both are saturated while the structure is still on, which usually means that the interlock is maintained until the equipment is turned off.

The SEL (Single Event Latch-up) are detected by analyzing the feed current, and seeing if it exceeds a specific threshold (typically 5 to 10 times the nominal value). That is why each of the feeds must be monitored and controlled independently. Since the transistor generated can be very fast, this monitoring must be done with equipment that allows to capture these events (400MSPS and similar).

Additionally, as there are several pieces and these can be configured in different ways, the set-up will have to be designed to be able to manage a large number of events in parallel, so the implementation of an FPGA in the design of the project is foreseeable. draft.

Link to other activities:600

This project is part of the development of the laboratory for the characterization of electronic components against RadLab radiation.

Knowledge is required – experience in:

• Component electronics
• Laboratory instrumentation and GPIB protocol
• Labview
• Design of circuits and PCBs
• FPGAs

During the first week of the project Alter’s tutor will give specific training on a specific case, which will allow the student to limit the scope of this project based on the experience of the candidate and their familiarity with the work tools required.

The results of this previous project will serve as validation of the set-up that is designed in this new development.

The project will end with an operative set-up, functional and validated by Alter’s tutor and documented in the required detail so that it could be the basis of a maintenance plan for the application if necessary.

Time Limit: It is expected that this second phase of development will take 4 to 8 weeks of work, and that the deliverables will be approved by the tutors at the end of the project.

Expected result:

1. Design and manufacture of an SEL monitoring system.
2. Generation of the documentation associated with deliverable # 1.
3. Identification of improvement areas in case new versions were required.